1. Field of the Invention
The present invention relates to a frequency synthesizer mounted on a base station apparatus or communication terminal apparatus in a radio communication system and an oscillation frequency control method.
2. Description of the Related Art
A frequency synthesizer is mounted on a base station apparatus or communication terminal apparatus in a radio communication system in order to create a carrier wave of an arbitrary frequency from a reference signal.
The frequency synthesizer is required to have a short lockup time to reduce power consumption during intermittent reception. As a frequency synthesizer with a short lockup time, a frequency synthesizer according to a fractional N system is known, which with a time-variable frequency dividing ratio, controls the frequency dividing ratio so that an average of the frequency dividing ratio includes decimals.
The xe2x80x9clockup timexe2x80x9d refers to a time after a frequency dividing ratio is changed until the frequency of an output signal of a voltage control oscillator converges to a target frequency.
Hereinafter a conventional frequency synthesizer according to a fractional N system (hereinafter simply referred to as xe2x80x9cfrequency synthesizerxe2x80x9d) will be explained using the attached drawings. FIG. 1 is a block diagram showing a configuration of the conventional frequency synthesizer.
In FIG. 1, VCO (voltage control oscillator) 1 oscillates a signal of frequency fvco according to the voltage of an input signal. First frequency divider 2 divides frequency fvco of the output signal of VCO 1 based on the frequency dividing ratio input from frequency dividing ratio control circuit 7, which will be described later, and outputs a signal of frequency fdiv.
Oscillator 3 oscillates a reference signal of frequency fosc. Second frequency divider 4 divides frequency fosc of the reference signal with a fixed frequency dividing ratio and outputs a signal of frequency fref. When locked, frequency fdiv of the output signal of first frequency divider 2 is equal to frequency fref of the output signal of second frequency divider 4.
Phase comparator 5 compares the phase of the output signal of first frequency divider 2 with the phase of the output signal of second frequency divider 4 and calculates the phase difference. LPF (low-pass filter) 6 averages the output value of phase comparator 5 and outputs the average result to VCO 1. This removes the AC component from the output value of phase comparator 105 and only a signal with the DC component is input to VCO 1.
Frequency dividing ratio control circuit 7 calculates a frequency dividing ratio to be output to first frequency divider 2 using the output signal of first frequency divider 2 as a clock. At this time, frequency dividing ratio control circuit 7 controls the frequency dividing ratio so that the frequency dividing ratio is time-variable and the average value of the frequency dividing ratio includes decimals.
Next, an internal configuration of frequency dividing ratio control circuit 7 in the conventional frequency synthesizer disclosed in the International Publication No.WO92/04766 will be explained using a block diagram in FIG. 2.
As shown in FIG. 2, frequency dividing ratio control circuit 7 in the conventional frequency synthesizer is mainly configured by a plurality of cascaded accumulators 11, delay circuits 12 that delay carry-out signals output from accumulators 11 and adder 13 that adds up the output signals of delay circuits 12.
In FIG. 2, the number of accumulators 11 used is xe2x80x9c4xe2x80x9d and the number of delay circuits 12 is xe2x80x9c12xe2x80x9d for frequency dividing ratio control circuit 7, but the above described frequency synthesizer has no limitation on the number of accumulators 11 and the number of delay circuits 12.
Data K (K: integer) is input to accumulator 11-1 and data M (M: integer) is input to adder 13.
Accumulators 11-1 to 11-4 each use the output signal of first frequency divider 2 as a clock, accumulate the input data for every clock and output a carry-out signal when the accumulation result exceeds size L (L: integer) of the accumulators.
Adder 13 adds xe2x80x9c1xe2x80x9d to data M when a carry-out signal is input and adds nothing to data M when no carry-out signal is input. Then, adder 13 outputs the addition result to first frequency divider 2 as a frequency dividing ratio.
That is, the frequency dividing ratio becomes (M+1) at a rate of K/L, and M at a rate of (1xe2x88x92K/L). Therefore, average value Rave of the frequency dividing ratio is obtained from expression (1) below:                                                         Rave              =                                                                    (                                          M                      +                      1                                        )                                    xc3x97                                      K                    /                    L                                                  +                                  M                  xc3x97                                      (                                          1                      -                                              K                        /                        L                                                              )                                                                                                                          =                              M                +                                  K                  /                  L                                                                                        (        1        )            
where, M, L and K are all integers and K less than L, and therefore the average of the frequency dividing ratio Rave includes decimals.
Furthermore, frequency fvco of the output signal of VCO 1 is obtained from expression (2) below:                                                         fvco              =                                                (                                      M                    +                                          K                      /                      L                                                        )                                xc3x97                fdiv                                                                                        =                                                (                                      M                    +                                          K                      /                      L                                                        )                                xc3x97                fref                                                                        (        2        )            
Moreover, the relationship between desired frequency interval fstp necessary for output in VCO 1 and L is expressed in expression (3) below:
fstp=fref/Lxe2x80x83xe2x80x83(3)
As is clear from expression (3) above, frequency fref can be increased by increasing L.
As shown above, the frequency synthesizer according to the fractional N system can average its frequency dividing ratio by changing the frequency dividing ratio to be set in first frequency divider 2 with time in synchronization with frequency fdiv of the output signal of first frequency divider 2, and therefore frequency fvco need not be set to an integer multiple of frequency fref. Because of this, it is possible to set high frequency fref irrespective of desired frequency interval fstp in the output signal of VCO 1.
Then, it is possible to increase the loop gain of a PLL comprising the frequency synthesizer by setting high frequency fref, making it possible to shorten the lockup time.
Since a carry-out signal has periodicity and unnecessary spurious is generated on the output signal of VCO 1 if only accumulator 11-1 is used, accumulators 11-2 to 11-4 and delay circuits 12-1 to 12-12 are additionally provided to cancel out the periodic component and prevent unnecessary spurious.
However, the conventional frequency synthesizer above has a problem that L may become an integer multiple of K depending on frequency fvco of the output signal of VCO 1, in which case spurious different from the spurious above is generated. As a simple example of this, a case with K=2 and L=8 will be explained. Table 1 shows accumulation results of accumulators 11-1 to 11-4 for different clocks.
As shown in Table 1, the accumulation results of all accumulators become equal with clock 1 and clock 17, and a frequency component of fref/16 is generated. This frequency component appears as spurious with the output signal of VCO 1. To suppress spurious due to this frequency component, the time constant of the LPF must be increased, which will result in an increased lockup time.
Moreover, as described in the International Publication No.WO92/04766, it is desirable that size L (=fref/fstp) of an accumulator be power of 2 to simplify the circuit. On the contrary, the conventional frequency synthesizer above has a problem that there are cases where the frequency of a reference signal cannot be selected so that fref/fstp becomes power of 2.
As a countermeasure, a method of setting extremely high L (e.g., 24th power of 2) and slightly shifting frequency fvco from a desired frequency is known, but this method will increase the scale of circuit, resulting in increased power consumption.
It is an object of the present invention to provide a frequency synthesizer and oscillation frequency control method with a good spurious characteristic, a short lockup time and small power consumption.
The present invention attains the above object by randomly changing a frequency dividing ratio by adding a random signal to a carry-out signal and converting spurious to white noise.